PRU-0
;*
;* Copyright (C) 2016 Zubeen Tolani <ZeekHuge - [email protected]>
;* IMDEA NETWORKS Institute: This file has been modified and it is part of the OpenVLC's source codes
;* This file is as an example to show how to develope
;* and compile inline assembly code for PRUs
;*
;* This program is free software; you can redistribute it and/or modify
;* it under the terms of the GNU General Public License version 2 as
;* published by the Free Software Foundation.
;* define PRU0_R31_VEC_VALID 32
.asg 32, PRU0_R31_VEC_VALID ;* allows notification of program completion
;*#define PRU_EVTOUT_0 3
.asg 3, PRU_EVTOUT_0 ;* the event number that is sent back
.cdecls "main_pru0.c"
.clink
.global START0
START0: ; 5 Instructions - 1 not done before
; Enable the OCP master port -- allows transfer of data to Linux userspace
LBCO &r0, C4, 4, 4 ; load SYSCFG reg into r0 (use c4 const addr) #Load Byte Burst with Constant Table Offset (read a block of data from memory into the register file.)
CLR r0, r0, 4 ; clear bit 4 (STANDBY_INIT)
SBCO &r0, C4, 4, 4 ; store the modified r0 back at the load addr #Store Byte Burst with Constant Table Offset
#Read a data from data from C4 to register r0----then clear the register r0 then store modified r0 to C4
CLR r30, r30.t0
LDI32 r5, 0x00000FFF ; Mask
LDI32 r6, 0x00010000 ; Address memory where PRU1 store the address of new sample
LDI32 r4, 0x00011FFF ; Address limit
#Register different address to register r5,r6,r4
RESTART:
LDI32 r1, 0x00010004
;;;;;;;;;;;;;;; RX Code ;;;;;;;;;;;;;;; **performs signal sampling**
GET_SAMPLE:
LDI32 r7, 7 ; x - 110 instructions (55)
CLR r30, r30.t0 ; set the CS line low (active low)
SET r30, r30.t3
QBBC ZERO1, r31, 2 #Quick Branch if Bit is Clear
OR r3, r3, 0x00000001 #Performs 32-bit logical OR on two 32 bit zero extended source value
;JMP CONT_RX1
ZERO1:
;OR r3, r3, 0x00000000
;JMP CONT_RX1
CONT_RX1:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO2, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX2
ZERO2:
;OR r3, r3, 0x00000000
;JMP CONT_RX2
CONT_RX2:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO3, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX3
ZERO3:
;OR r3, r3, 0x00000000
;JMP CONT_RX3
CONT_RX3:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO4, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX4
ZERO4:
;OR r3, r3, 0x00000000
;JMP CONT_RX4
CONT_RX4:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO5, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX5
ZERO5:
;OR r3, r3, 0x00000000
;JMP CONT_RX5
CONT_RX5:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO6, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX6
ZERO6:
;OR r3, r3, 0x00000000
;JMP CONT_RX6
CONT_RX6:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO7, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX7
ZERO7:
;OR r3, r3, 0x00000000
;JMP CONT_RX7
CONT_RX7:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO8, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX8
ZERO8:
;OR r3, r3, 0x00000000
;JMP CONT_RX8
CONT_RX8:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO9, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX9
ZERO9:
;OR r3, r3, 0x00000000
;JMP CONT_RX9
CONT_RX9:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO10, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX10
ZERO10:
;OR r3, r3, 0x00000000
;JMP CONT_RX10
CONT_RX10:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO11, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX11
ZERO11:
;OR r3, r3, 0x00000000
;JMP CONT_RX11
CONT_RX11:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO12, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX12
ZERO12:
;OR r3, r3, 0x00000000
;JMP CONT_RX12
CONT_RX12:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO13, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX13
ZERO13:
;OR r3, r3, 0x00000000
;JMP CONT_RX13
CONT_RX13:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO14, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX14
ZERO14:
;OR r3, r3, 0x00000000
;JMP CONT_RX14
CONT_RX14:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO15, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX15
ZERO15:
;OR r3, r3, 0x00000000
;JMP CONT_RX15
CONT_RX15:
CLR r30, r30.t3
LSL r3, r3, 1
SET r30, r30.t3
QBBC ZERO16, r31, 2
OR r3, r3, 0x00000001
;JMP CONT_RX16
ZERO16:
;OR r3, r3, 0x00000000
;JMP CONT_RX16
CONT_RX16:
CLR r30, r30.t3
SET r30, r30.t0 ; pull the CS line high (end of sample)
LSR r3, r3, 2 ; SPICLK shifts left too many times left, shift right once
AND r3, r3, r5 ; AND the data with mask to give only the 10 LSBs
; Save the data in the shared memory
SBBO &r3, r1, 0, 4 #Store Byte Burst to r1
SBBO &r1, r6, 0, 4 #Store Byte Burst to r6
ADD r1, r1, 4
;sub r7, r7, 55
NOT_RESTART:
; Received 72 = 144 instructions (each 1 received add 2 instructions so 80 (160 instructions))
;ADD r7, r7, 11
;WAIT: ; 3 (not taking into account wait)
;SUB r7, r7, 1
;QBNE WAIT, r7, 0 #Quick Branch if Not Equal
QBGE RESTART, r4, r1 #Quick Branch if Greater Than or Equal
JMP GET_SAMPLE
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;/
HALT
PRU-1
;* IMDEA NETWORKS Institute: This file has been modified and it is part of the OpenVLC's source codes
.asg 32, PRU0_R31_VEC_VALID ;* allows notification of program completion
;*#define PRU_EVTOUT_0 3
.asg 3, PRU_EVTOUT_0 ;* the event number that is sent back
.cdecls "main_pru1.c"
.clink
.global START1
START1:
RESTART:
; Enable the OCP master port -- allows transfer of data to Linux userspace
LBCO &r0, C4, 4, 4 ; load SYSCFG reg into r0 (use c4 const addr) #Load Byte Burst with Constant Table Offset
CLR r0, r0, 4 ; clear bit 4 (STANDBY_INIT)
SBCO &r0, C4, 4, 4 ; store the modified r0 back at the load addr #Store Byte Burst with Constant Table Offset
LDI32 r1, 0x00002000 ; load the base address into r1
LDI32 r2, 0x00000000 ; Sample
LDI32 r3, 0x00010004 ; Memory of new sample
LDI32 r4, 0x00010000 ; Address of shared memory flag
LDI32 r5, 0x00000000 ; Number of equal samples
LDI32 r6, 0x000000FF ; Mask
LDI32 r7, 0x00000000 ; Symbols to add (LSB)
LDI32 r8, 0x00000000 ; Last sample (decoded)
LDI32 r9, 0x00000000 ; Actual sample (decoded)
LDI32 r10, 0x00000000
LDI32 r12, 0x00000000 ; 32 - symbols group
LDI32 r13, 0x00000000 ; Symbols in last register
LDI32 r14, 32 ; Number of bits per memory address
LDI32 r15, 0xAAAAAAAA ; Preamble
LDI32 r16, 0x00000000 ; Temporary pointer register
LDI32 r17, 0x00000000 ; Reg storing samples counter
LDI32 r18, 1021 ; Threshold 803 (75kohm)
LDI32 r19, 0x00000000 ; Manchester decoded bit
LDI32 r20, 0x00000000 ;Current symbol
SBBO &r20, r1, 0, 4
LDI32 r21, 0x00000000 ;Next symbol
LDI32 r24, 0x00000000 ; Symbols for the length
LDI32 r25, 0x00000000 ;Preamble
LDI32 r26, 0x00000000 ; Length
LDI32 r27, 0x000000A3 ; SFD
LDI32 r28, 0x00000000 ; bit 0 flag for bit slip
LDI32 r29, 0x00000000 ; Zero register
clr r30, r30.t12
;;;;;;;;; GET PREAMBLE ;;;;;;;;;
; GET_PREAMBLE:
; JAL r11.w0, GET_SAMPLE #Unconditional Jump and Link (Unconditional jump to a 16 bit instruction address, specified by register or immediate valu)
; LSL r25, r25, 1 #Logical Shift Left
; QBBC PREAMBLE_ZERO, r8, 0 #Quick Branch if Bit is Clear
; SET r25, r25.t0
; PREAMBLE_ZERO:
; QBEQ PREAMBLE_DETECTED, r25, r15 #Quick Branch if Equal
; JMP GET_PREAMBLE
PREAMBLE_DETECTED:
;;;;;;;;; GET SFD ;;;;;;;;;
set r30, r30.t10
JAL r11.w0, GET_SAMPLE
QBBC NO_NEW_BIT1, r28, 0 #Quick Branch if Bit is Clear
LSL r25, r25, 1
ADD r25, r25, r10
CLR r28, r28.t0
AND r25, r25, r6
NO_NEW_BIT1:
;;;;;;;;;;;;;;;;;;;;;;;;;;;
QBEQ SFD_DETECTED, r25, r27
JMP PREAMBLE_DETECTED
SFD_DETECTED:
clr r30, r30.t10
;;;;;;;;; GET LENGTH ;;;;;;;;;
GET_LENGTH:
JAL r11.w0, GET_SAMPLE #Unconditional Jump and Link
QBBC NO_NEW_BIT2, r28, 0
ADD r24, r24, 1
LSL r26, r26, 1
ADD r26, r26, r10
CLR r28, r28.t0
NO_NEW_BIT2:
QBEQ LENGTH_OBTAINED, r24, 16
JMP GET_LENGTH
LENGTH_OBTAINED:
;;;;;;;;; STORE DATA ;;;;;;;;;
set r30, r30.t12
LDI32 r1, 0x00002004
QBGT RESTART, r26, 200 #Quick Branch if Greater Than
LDI32 r17, 32000
QBLT RESTART, r26, r17 #Quick Branch if Less Than
SBBO &r26, r1, 0, 4
SUB r26, r26, 81 ; this must be change with the tx
LSR r26, r26, 1
LDI32 r17, 0x00000000
ADD r1, r1, 4
set r30, r30.t9
STORE_DATA:
JAL r11.w0, GET_SAMPLE
QBBC NO_NEW_BIT3, r28, 0
CLR r28, r28.t0
SUB r26, r26, 1
LSL r12, r12, 1
ADD r12, r12, r10
ADD r17, r17, 1
NO_NEW_BIT3:
QBNE STORE_DATA, r17, 32 #Quick Branch if Not Equal
LDI32 r17, 0x00000000
SBBO &r12.b3, r1, 0, 4 ; store the value r2 in memory
SBBO &r12.b2, r1, 1, 4 ; store the value r2 in memory
SBBO &r12.b1, r1, 2, 4 ; store the value r2 in memory
SBBO &r12.b0, r1, 3, 4 ; store the value r2 in memory
LDI32 r12, 0x00000000
ADD r1, r1, 4
QBLE LAST_REG, r14, r26
JMP STORE_DATA
LAST_REG:
SUB r13, r14, r26
LAST_BITS:
JAL r11.w0, GET_SAMPLE
QBBC NO_NEW_BIT4, r28, 0
CLR r28, r28.t0
SUB r26, r26, 1
LSL r12, r12, 1
ADD r12, r12, r10
NO_NEW_BIT4:
QBNE LAST_BITS, r26, 0
LSL r12, r12, r13
SBBO &r12.b3, r1, 0, 4 ; store the value r2 in memory
SBBO &r12.b2, r1, 1, 4 ; store the value r2 in memory
SBBO &r12.b1, r1, 2, 4 ; store the value r2 in memory
SBBO &r12.b0, r1, 3, 4 ; store the value r2 in memory
LDI32 r12, 0x00000000
LDI32 r1, 0x00002000
LDI32 r20, 1
SBBO &r20, r1, 0,4
WAIT_FOR_US_TO_READ:
LBBO &r20,r1, 0, 4
QBNE WAIT_FOR_US_TO_READ,r20,0
clr r30, r30.t9
JMP RESTART
GET_SAMPLE:
;; Get a sample ;;
LBBO &r3, r4, 0,4 ; Load memory of new sample
QBEQ GET_SAMPLE, r3, 0 ; Check if there is new sample to be read
LBBO &r2, r3, 0, 4 ; Load the sample
SBBO &r29, r4, 0, 4 ; Clean the flag
;; Decode the sample
QBLT SAMPLE_ZERO, r18, r2
LDI32 r9, 0x00000001
JMP CONT
SAMPLE_ZERO:
LDI32 r9, 0x00000000
CONT:
;; Decode the samples
QBEQ EQUAL, r8, r9
QBBS FLAG_ACTIVE, r28, 1 #Quick Branch if Bit is Set
MOV r10, r9 ;; Pass the actual value (Man decoded)
SET r28, r28.t0 ;; Set the flag
SET r28, r28.t1 ;; Set the flag
LDI32 r7, 0x00000001 ;; Reset the counter
MOV r8, r9 ;; Shift data register
JMP r11.w0
FLAG_ACTIVE:
QBGE NO_NEW_SYMBOL, r7, 3 #Quick Branch if Greater Than
MOV r10, r9 ;; Pass the actual value (Man decoded)
SET r28, r28.t0 ;; Set the flag
LDI32 r7, 0x00000001 ;; Reset the counter
MOV r8, r9 ;; Shift data register
JMP r11.w0
NO_NEW_SYMBOL:
CLR r28, r28.t1 ;; Reset the flag
LDI32 r7, 0x00000001 ;; Reset the counter
MOV r8, r9 ;; Shift data register
JMP r11.w0
EQUAL:
ADD r7, r7, 1
MOV r8, r9
JMP r11.w0